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19-1206; Rev 0; 3/97
+2.5V to +5.5V, Low-Power, Single/Dual, 8-Bit Voltage-Output DACs in MAX Package
_______________General Description
The MAX548A/MAX549A/MAX550A serial, 8-bit voltageoutput digital-to-analog converters (DACs) operate from a single +2.5V to +5.5V supply. Their 1LSB TUE specification is guaranteed over temperature. Operating current (supply current plus reference current) is typically 75A per DAC with VDD = 2.5V. In shutdown, the DAC is disconnected from the reference, reducing current drain to less than 1A. The MAX548A/MAX549A allow each DAC to be shut down independently. The 10MHz, 3-wire serial interface is compatible with SPITM/QSPITM and MicrowireTM interface standards. Double-buffered inputs provide flexibility when updating the DACs; the input and DAC registers can be updated individually or simultaneously. The MAX548A is a dual DAC with an asynchronous load input; it uses VDD as the reference input. The MAX549A is a dual DAC with an external reference input. The MAX550A is a single DAC with an external reference input and an asynchronous load input. The MAX548A/MAX549A/MAX550A's low power consumption and small MAX and DIP packages make these devices ideal for portable and battery-powered applications.
____________________________Features
o +2.5V to +5.5V Single-Supply Operation o 1LSB (max) TUE o Power-On Reset Clears All Registers to Zero o Low Operating Current: 150A (MAX548A/MAX549A, VREF = +2.5V) 75A (MAX550A, VREF = +2.5V) o 1A Shutdown Mode o 10MHz, 3-Wire Serial Interface Compatible with SPI/QSPI and Microwire o MAX Package--50% Smaller than 8-Pin SO o Independent Shutdown of DACs (MAX548A/MAX549A)
MAX548A/MAX549A/MAX550A
______________Ordering Information
PART MAX548ACPA MAX548ACUA MAX548AC/D MAX548AEPA MAX548AEUA TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C PIN-PACKAGE 8 Plastic DIP 8 MAX Dice* 8 Plastic DIP 8 MAX
________________________Applications
Battery-Powered Systems VCXO Control Comparator-Level Settings GaAs Amp Bias Control Digital Gain and Offset Control
Ordering Information continued at end of data sheet. *Dice are specified at TA = +25C, DC parameters only. Contact factory for availability of 8-pin SO package.
_____________________Selector Guide
FEATURE Number of DACs DAC Reference Asynchronous Load DAC Input MAX Package MAX548A 2 VDD MAX549A 2 External -- MAX550A 1 External
_________________Pin Configurations
TOP VIEW
GND 1 OUTA 2 8 7 VDD OUTB LDAC SCLK
MAX548A
CS 3 DIN 4 6 5
DIP/MAX
SPI and QSPI are trademarks of Motorola Inc. Microwire is a trademark of National Semiconductor Corp.
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
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+2.5V to +5.5V, Low-Power, Single/Dual, 8-Bit Voltage-Output DACs in MAX Package MAX548A/MAX549A/MAX550A
ABSOLUTE MAXIMUM RATINGS
VDD, SCLK, DIN, CS, LDAC, OUT_ to GND ...............-0.3V to 6V REF to GND ................................................-0.3V to (VDD + 0.3V) Maximum Current (any pin) .............................................50mA Continuous Power Dissipation (TA = +70C) Plastic DIP (derate 9.09mW/C above +70C) .............727mW MAX (derate 4.10mW/C above +70C) .....................330mW Operating Temperature Ranges MAX5_ _AC_ A.....................................................0C to +70C MAX5_ _AE_ A ..................................................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER STATIC PERFORMANCE Resolution Differential Nonlinearity Total Unadjusted Error Zero-Code Error Full-Scale Error REFERENCE INPUT Reference Input Voltage Range Reference Input Resistance DAC Code = 55 Hex (Note 2) Reference Input Current DAC Code = 55 Hex (Note 3) DAC OUTPUT DAC Output Voltage Swing DAC Output Resistance DAC Output Resistance Matching DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current Input Capacitance (Note 4) VIH VIL IIN CIN VIN = 0V or VDD 0.7VDD 0.3VDD 1 10 V V A pF ROUT ROUT/ ROUT MAX548A/MAX549A MAX548A MAX549A/MAX550A 0 0 33.3 0.2 VDD VREF V k % VREF RREF MAX549A/MAX550A for specified performance MAX549A MAX550A MAX549A IREF MAX550A VDD = VREF = 5.5V VDD = VREF = 2.5V VDD = VREF = 5.5V VDD = VREF = 2.5V 2.5 16.7 33.3 330 150 165 75 550 250 275 125 A VDD V k N DNL TUE ZCE FSE Guaranteed monotonic MAX5_ _AEUA (Note 1) All others MAX5_ _AEUA (Note 1) All others 8 0.9 0.9 1 1 1 1 Bits LSB LSB LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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+2.5V to +5.5V, Low-Power, Single/Dual, 8-Bit Voltage-Output DACs in MAX Package
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C) PARAMETER DYNAMIC PERFORMANCE Digital Feedthrough and Crosstalk Voltage-Output Settling Time Voltage-Output Slew Rate Wake-Up Time at Power-Up POWER SUPPLIES Supply Voltage Range Supply Current (MAX548A) Supply Current (MAX549A/MAX550A) Shutdown Current VDD IDD Outputs unloaded, all inputs = GND or VDD Outputs unloaded, all inputs = GND or VDD (Note 5) VDD = 5.5V VDD = 2.5V 2.5 330 150 0.3 0.3 5.5 550 A 250 10 A A V CS = high, all digital inputs from 0V to VDD To 1/2LSB, CL = 20pF CL = 20pF CL = 20pF VDD = 2.5V VDD = 5.5V 50 4 1.4 3.1 4 nV-sec s V/s s SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX548A/MAX549A/MAX550A
IDD
Outputs unloaded, all inputs = GND or VDD; VDD = 5.5V Shutdown mode
TIMING CHARACTERISTICS
(VDD = +2.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Digital inputs switching from 0V to VDD.) (Figure 3) (Note 4) PARAMETER SCLK Pulse Width High SCLK Pulse Width Low DIN to SCLK High Setup DIN to SCLK High Hold CS Low to SCLK High Setup CS High to SCLK High Setup SCLK High to CS Low Hold Delay, SCLK High to CS High CS Pulse Width High SCLK Period LDAC Pulse Width Low CS High to LDAC Low VDD High to CS Low Note 1: Note 2: Note 3: Note 4: Note 5: SYMBOL tCH tCL tDS tDH tCSS0 tCSS1 tCSH0 tCSH1 tCSW tCP t LDAC tCSLD MAX548A/MAX550A only MAX548A/MAX550A only VDD = 2.5V VDD = 5.5V VDD = 2.5V VDD = 5.5V CONDITIONS MIN 40 40 30 0 10 30 30 10 10 20 40 80 50 50 5 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns s
Cold temperature specifications (to -40C) guaranteed by design using six sigma design limits. Worst-case input resistance at REF occurs at DAC code 55 hex. Worst-case reference input current occurs at DAC code 55 hex. Guaranteed by design. Not production tested. IDD measured with DACs loaded with worst-case DAC code 55 hex.
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+2.5V to +5.5V, Low-Power, Single/Dual, 8-Bit Voltage-Output DACs in MAX Package MAX548A/MAX549A/MAX550A
__________________________________________Typical Operating Characteristics
(VDD = VREF = 2.5V, RL = 1M, CL = 15pF, TA = +25C, unless otherwise noted.)
OPERATING CURRENT PER DAC vs. TEMPERATURE
MAX548A-550A TOC-01
SHUTDOWN CURRENT vs. TEMPERATURE
200 SHUTDOWN CURRENT (nA) 160 120 40 36 32 28 VDD = VREF = 2.5V -60 -20 20 TEMPERATURE (C) 60 100 VDD = VREF = 5.0V
MAX548A-550A TOC-02
240
150.2 OPERATING CURRENT PER DAC (A) 149.8 149.4 75.4 75.0 VDD = VREF = 2.5V 74.6 -60 -20 20 TEMPERATURE (C) 60 VDD = VREF = 5.0V
100
MAX549A/MAX550A REFERENCE SMALL-SIGNAL FREQUENCY RESPONSE
MAX548A-550A TOC-03
MAX549A/MAX550A REFERENCE AC FEEDTHROUGH vs. FREQUENCY
MAX548A-550A TOC-04
10 0 RELATIVE OUTPUT (dB) -10 -20 -30 -40 -50 1k
VDD = 2.5V VREF = 100mVp-p SINE WAVE
0
-20 RELATIVE OUTPUT (dB)
VDD = 5V VREF = 2Vp-p SINE WAVE
-40
-60
-80 DAC CODE = FF hex 10k 100k FREQUENCY (Hz) 1M 10M VREF = 1Vp-p SINE WAVE DAC CODE = 00 hex -100 10 100 1k 10k 100k 1M FREQUENCY (Hz)
DIGITAL FEEDTHROUGH
MAX548A-550A TOC-05
SETTLING TIME (FALLING)
DAC CODE FF hex to 00 hex
MAX548A-550A TOC-06
SCLK, 5V/div
OUT, 1V/div
OUT, 50mV/div
CS, 5V/div
200ns/div
2s/div
4
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+2.5V to +5.5V, Low-Power, Single/Dual, 8-Bit Voltage-Output DACs in MAX Package
_____________________________Typical Operating Characteristics (continued)
(VDD = VREF = 2.5V, RL = 1M, CL = 15pF, TA = +25C, unless otherwise noted.)
MAX548A/MAX549A/MAX550A
OUTPUT GLITCH FILTERING
MAX548A-550A TOC-07
SETTLING TIME (RISING)
DAC CODE 00 hex to FF hex
MAX548A-550A TOC-08
CODE = 00 hex
OUT, 50mV/div, CL = 0pF OUT, 50mV/div, CL = 100pF OUT, 50mV/div, CL = 220pF OUT, 50mV/div, CL = 1000pF CS, 5V/div
OUT, 1V/div
CS, 5V/div
5s/div
2s/div
______________________________________________________________Pin Description
PIN MAX548A 1 2 -- 3 MAX549A 1 2 -- 3 MAX550A 1 -- 2 3 NAME GND OUTA OUT CS Ground DAC A Output Voltage DAC Output Voltage Chip-Select Input. A logic low on CS enables serial data to be clocked into the input shift register. Programming commands are executed at CS's rising edge. Serial-Data Input. Data is clocked into the 16-bit input shift register on SCLK's rising edge. Serial-Clock Input. Data is clocked in on SCLK's rising edge. Load DAC Input. After CS goes high and if programmed by the control word, a falling edge on LDAC updates the DAC latch(es). Connect LDAC to VDD if unused. DAC B Output Voltage External Reference Voltage Input for DAC(s) Positive Power Supply (+2.5V to +5.5V) FUNCTION
4 5
4 5
4 5
DIN SCLK LDAC
6
--
6
7 -- 8
6 7 8
-- 7 8
OUTB REF VDD
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+2.5V to +5.5V, Low-Power, Single/Dual, 8-Bit Voltage-Output DACs in MAX Package MAX548A/MAX549A/MAX550A
_______________Detailed Description
Analog Section
The MAX548A/MAX549A/MAX550A are 8-bit, voltageoutput digital-to-analog converters (DACs). The MAX548A/MAX549A are dual DACs, and the MAX550A is a single DAC. Each DAC consists of an R-2R ladder network that converts 8-bit digital inputs into equivalent analog output voltages in proportion to the applied reference voltage (Figure 1). The DACs feature double-buffered inputs and unbuffered outputs. The MAX549A/MAX550A require an external reference. The MAX548A's reference inputs are internally connected to VDD . The power-supply range is from +2.5V to +5.5V. The magnitude of the expected error is the ratio of the DAC output resistance to the DC load resistance at the output. Typically, an energy pulse is coupled into the DAC output on CS's rising edge. Since each DAC output is unbuffered, connecting a small capacitor (200pF to 1000pF) from the output to ground creates a lowpass filter that effectively suppresses the pulse for sensitive applications (see Typical Operating Characteristics).
Reference Input The voltage applied at REF (VDD for the MAX548A) sets the full-scale output for all the DACs and may range from +2.5V to VDD. The REF input resistance is code dependent, with the lowest value occurring with code 01010101 (55 hex). To minimize INL errors, the reference voltage source should have less than 3 output impedance. DAC Output The MAX548A/MAX549A/MAX550A contain DACs with unbuffered outputs; each output connects directly to an R-2R ladder. Typical output impedance is 33.3k. This configuration minimizes power consumption and reduces offset errors. For highest accuracy, apply high resistive loads (1M and up). Lower resistive loads can be driven, but output loading increases full-scale error.
Shutdown Mode When the MAX548A/MAX549A/MAX550A are in shutdown mode, the R-2R ladder disconnects from the reference source. The MAX549A/MAX550A supply current does not change, but the REF input current decreases to less than 1A. This allows the externally applied system reference to remain active with minimal power consumption. The MAX548A supply current also decreases to less than 1A in shutdown mode. When the MAX548A/MAX549A/MAX550A exit shutdown mode, recovery time is equivalent to the DAC's settling time.
Serial Interface
The serial interface is SPI/QSPI and Microwire compatible. An active-low chip select (CS) enables the input shift register to receive data from the serial input (DIN). Data is clocked into the shift register on the rising edge of the serial-clock signal (SCLK). The clock frequency can be as high as 10MHz. Transmit data MSB first in one 16-bit word or two 8-bit bytes. The write cycle can be segmented to allow two 8-bit-wide transfers when CS remains low. After all 16 bits are clocked into the input shift register, a rising
R
R
R
R
R
R
R
2R
2R
2R
2R
2R
2R
2R
2R
2R
REF GND LSB DAC_ REGISTER NOTE: SWITCH POSITIONS SHOWN FOR DAC CODE FF HEX. MSB
OUT_ GND
Figure 1. DAC Simplified Circuit Diagram
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+2.5V to +5.5V, Low-Power, Single/Dual, 8-Bit Voltage-Output DACs in MAX Package
edge on CS programs the DAC. The input registers can be loaded independently or simultaneously without updating the DAC registers. This allows both DAC registers to be updated simultaneously with different digital values. The DAC outputs reflect the data stored in the DAC registers. LDAC can be used to asynchronously update the DAC registers independently of CS (MAX548A/MAX550A). With C1 set high, setting C0 in the control word forces the DAC register(s) to be updated on LDAC's falling edge, rather than CS's rising edge (Table 1).
Initialization The MAX548A/MAX549A/MAX550A have an internal power-on reset. At power-up, all internal registers are reset to zero; therefore, an initialization write sequence is not necessary.
Serial-Input Data Format and Control Codes The control byte determines which input registers/DAC registers are updated (Table 1). The DAC input registers are updated on the rising edge of CS. The DAC registers can be updated on CS's rising edge or on LDAC's falling edge after CS goes high. Bit C0 of the control byte determines how the DAC registers are updated for the MAX548A/MAX550A. The MAX549A has no LDAC pin; the DAC registers are always updated on CS's rising edge (C0 in the control byte has no effect). Tables 2, 3, and 4 list the serial-input command format for the MAX548A, MAX549A, and MAX550A, respectively. The 16-bit input word consists of an 8-bit control byte and an 8-bit data byte. The control byte is not decoded internally. Every control bit performs one
MAX548A/MAX549A/MAX550A
Table 1. Control-Byte/Input-Word Bit Definitions
BIT NAME UB1* UB2 UB3 C2 C2 C1 CONTROL BYTE C1 C0 C0 A1 A1 A0 A0 D7 D6 D5 DATA BYTE D4 D3 D2 D1 D0** X = Don't care *Clocked in first STATE X X X 0 1 0 1 0 1 0 1 0 1 -- -- -- -- -- -- -- -- **Clocked in last 7 Unassigned Bit 1 Unassigned Bit 2 Unassigned Bit 3 Power-Up Mode Power-Down Mode DAC Register Load Operation Disabled DAC Register Load Operation Enabled DAC Register Updated on CS's Rising Edge DAC Register Updated on LDAC's Falling Edge (MAX549A = Don't Care) Do Not Address DAC B (MAX550A = Don't Care) Address DAC B (MAX550A = Don't Care) Do Not Address DAC A Address DAC A DAC Data Bit 7 (MSB) DAC Data Bit 6 DAC Data Bit 5 DAC Data Bit 4 DAC Data Bit 3 DAC Data Bit 2 DAC Data Bit 1 DAC Data Bit 0 (LSB) OPERATION
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+2.5V to +5.5V, Low-Power, Single/Dual, 8-Bit Voltage-Output DACs in MAX Package MAX548A/MAX549A/MAX550A
function. Data is clocked in starting with unassigned bit 1 (UB1), followed by the remaining control bits and the DAC data byte. The data byte's LSB (D0) is the last bit clocked into the input register (Figure 2). Table 5 is an example of a 16-bit input word that performs the following functions: * Loads 80 hex (128 decimal) into the DAC input register (DAC A for the MAX548A/MAX549A) * Updates the DAC register(s) on CS's rising edge. Table 6 shows how to calculate the output voltage based on the input code. Figure 3 gives detailed timing information.
INSTRUCTION EXECUTED CS
LDAC MAX548A/ MAX550A ONLY 1 SCLK DIN UB1 UB2 UB3 C2 C1 C0 A1 A0 8
OPTIONAL PAUSE
9
16
D7
D6
D5
D4
D3
D2
D1
D0
Figure 2. Serial-Interface Timing Diagram
tLDAC LDAC tCSLD
CS
tCSH0 tCSS0 tCH tCSH1
tCSW
SCLK
tDS tDH
tCL
tCSS1
DIN
Figure 3. Detailed Serial-Interface Timing Diagram
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+2.5V to +5.5V, Low-Power, Single/Dual, 8-Bit Voltage-Output DACs in MAX Package
Table 2. MAX548A Serial-Interface Programming Commands
CONTROL BYTE Loaded First UB1 X X UB2 X X UB3 X X C2 0 1 C1 0 X C0 X X A1 0 0 A0 0 0 UNASSIGNED COMMANDS XXXXXXXX XXXXXXXX X X Unassigned command Unassigned operation Load DAC A input register. DAC B input register and both DAC registers unchanged. Load DAC B input register. DAC A input register and both DAC registers unchanged. Load both DAC input registers. Both DAC registers unchanged. Update both DAC registers with current contents of their input registers. Both input registers unchanged. Load DAC A input register and update both DAC registers. DAC B input register unchanged. Load DAC B input register and update both DAC registers. DAC A input register unchanged. Load both DAC input registers and update both DAC registers. Update both DAC registers with current contents of their input registers. Both input registers unchanged. Load DAC A input register and update both DAC registers. DAC B input register unchanged. Load DAC B input register and update both DAC registers. DAC A input register unchanged. Load both DAC input registers and update both DAC registers. After CS's rising edge and on LDAC's falling edge, update both DAC registers with current contents of their input registers. Both input registers unchanged. Load DAC A input register. After CS's rising edge and on LDAC's falling edge, update both DAC registers. Load DAC B input register. After CS's rising edge and on LDAC's falling edge, update both DAC registers. Load both DAC input registers. After CS's rising edge and on LDAC's falling edge, update both DAC registers. 9 DATA BYTE Loaded Last D7........D0 LDAC Pin 6 COMMAND (Commands executed on CS's rising edge)
MAX548A/MAX549A/MAX550A
COMMANDS LOADING INPUT REGISTER(S) ONLY X X X X X X X X X 0 0 0 0 0 0 X X X 0 1 1 1 0 1 8-Bit DAC Data 8-Bit DAC Data 8-Bit DAC Data X X X
COMMANDS UPDATING DAC REGISTER(S) X X X 0 1 0 0 0 XXXXXXXX X
X X X
X X X
X X X
0 0 0
1 1 1
0 0 0
0 1 1
1 0 1
8-Bit DAC Data 8-Bit DAC Data 8-Bit DAC Data
X X X
X
X
X
0
1
1
0
0
XXXXXXXX
0
X X X
X X X
X X X
0 0 0
1 1 1
1 1 1
0 1 1
1 0 1
8-Bit DAC Data 8-Bit DAC Data 8-Bit DAC Data
0 0 0
COMMANDS UTILIZING THE ASYNCHRONOUS LOAD FUNCTION
X
X
X
0
1
1
0
0
XXXXXXXX
1
X
X
X
0
1
1
0
1
8-Bit DAC Data
1
X
X
X
0
1
1
1
0
8-Bit DAC Data
1
X
X
X
0
1
1
1
1
8-Bit DAC Data
1
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+2.5V to +5.5V, Low-Power, Single/Dual, 8-Bit Voltage-Output DACs in MAX Package MAX548A/MAX549A/MAX550A
Table 2. MAX548A Serial-Interface Programming Commands (continued)
COMMANDS FOR POWERING DOWN
CONTROL BYTE Loaded First UB1 UB2 UB3 C2 C1 C0 A1 A0 DATA BYTE Loaded Last D7........D0 LDAC Pin 6 COMMAND (Commands executed on CS's rising edge)
COMMANDS POWERING DOWN AND LOADING INPUT REGISTER(S) ONLY X X X X X X X X X 1 1 1 0 0 0 X X X 0 1 1 1 0 1 8-Bit DAC Data 8-Bit DAC Data 8-Bit DAC Data X X X Load DAC A input register and power down DAC A. DAC B registers unchanged. Load DAC B input register and power down DAC B. DAC A registers unchanged. Load both DAC input registers and power down both DACs. Both DAC registers unchanged Load DAC A input register, power down DAC A, and update both DAC registers. DAC B input register unchanged. Load DAC B input register, power down DAC B, and update both DAC registers. DAC A input register unchanged. Load both DAC input registers, power down both DACs, and update both DAC registers. Load DAC A input register, power down DAC A, and update both DAC registers. DAC B input register unchanged. Load DAC B input register, power down DAC B, and update both DAC registers. DAC A input register unchanged. Load both DAC input registers and power down both DACs. Update both DAC registers. Load DAC A input register and power down DAC A. While powered down, on LDAC's falling edge, update both DAC registers. DAC B input register unchanged. Load DAC B input register and power down DAC B. While powered down, on LDAC's falling edge, update both DAC registers. DAC A input register unchanged. Load both DAC input registers and power down both DACs. While powered down, on LDAC's falling edge, update both DAC registers.
COMMANDS POWERING DOWN AND UPDATING DAC REGISTER(S) X X X 1 1 0 0 1 8-Bit DAC Data X
X
X
X
1
1
0
1
0
8-Bit DAC Data
X
X
X
X
1
1
0
1
1
8-Bit DAC Data
X
X
X
X
1
1
1
0
1
8-Bit DAC Data
0
X
X
X
1
1
1
1
0
8-Bit DAC Data
0
X
X
X
1
1
1
1
1
8-Bit DAC Data
0
COMMANDS POWERING DOWN AND UTILIZING THE ASYNCHRONOUS LOAD FUNCTION
X
X
X
1
1
1
0
1
8-Bit DAC Data
1
X
X
X
1
1
1
1
0
8-Bit DAC Data
1
X
X
X
1
1
1
1
1
8-Bit DAC Data
1
X = Don't care
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+2.5V to +5.5V, Low-Power, Single/Dual, 8-Bit Voltage-Output DACs in MAX Package
Table 3. MAX549A Serial-Interface Programming Commands
CONTROL BYTE Loaded First UB1 X X X X UB2 X X X X UB3 X X X X C2 X 0 0 0 C1 0 0 0 0 C0 X X X X A1 0 0 1 1 A0 0 1 0 1 UNASSIGNED COMMAND XXXXXXXX 8-Bit DAC Data 8-Bit DAC Data 8-Bit DAC Data Unassigned command Load DAC A input register. DAC registers unchanged. Load DAC B input register. DAC registers unchanged. Load both DAC input registers. DAC registers unchanged. Update both DAC registers with current contents of their input registers. Both input registers unchanged. Load DAC A input register and update both DAC registers. DAC B input register unchanged. Load DAC B input register and update both DAC registers. DAC A input register unchanged. Load both DAC input registers and update both DAC registers. Load DAC A input register and power down DAC A. DAC B input register and both DAC registers unchanged. Load DAC B input register and power down DAC B. DAC A input register and both DAC registers unchanged. Load both DAC input registers and power down both DACs. Both DAC registers unchanged. Load DAC A input register, power down DAC A, and update both DAC registers. DAC B input register unchanged. Load DAC B input register, power down DAC B, and update both DAC registers. DAC A input register unchanged. Load both DAC input registers, power down both DACs, and update both DAC registers. COMMANDS LOADING INPUT REGISTER(S) ONLY DATA BYTE Loaded Last D7........D0 COMMAND (Commands executed on CS's rising edge)
MAX548A/MAX549A/MAX550A
COMMANDS UPDATING DAC REGISTER(S) X X X X X X X X X X X X X 0 0 0 1 1 1 1 X X X X 0 0 1 1 0 1 0 1 XXXXXXXX 8-Bit DAC Data 8-Bit DAC Data 8-Bit DAC Data
COMMANDS POWERING DOWN AND LOADING INPUT REGISTER(S) ONLY X X X X X X X X X 1 1 1 0 0 0 X X X 0 1 1 1 0 1 8-Bit DAC Data 8-Bit DAC Data 8-Bit DAC Data
COMMANDS POWERING DOWN AND UPDATING DAC REGISTER(S) X X X 1 1 X 0 1 8-Bit DAC Data
X
X
X
1
1
X
1
0
8-Bit DAC Data
X
X
X
1
1
X
1
1
8-Bit DAC Data
X = Don't care
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+2.5V to +5.5V, Low-Power, Single/Dual, 8-Bit Voltage-Output DACs in MAX Package MAX548A/MAX549A/MAX550A
Table 4. MAX550A Serial-Interface Programming Commands
CONTROL BYTE Loaded First UB1 X X X UB2 X X X UB3 X X X C2 0 1 0 C1 0 X 0 C0 X X X A1 X X X A0 0 0 1 UNASSIGNED COMMANDS XXXXXXXX XXXXXXXX 8-Bit DAC Data X X X Unassigned command Unassigned operation Load DAC input register. DAC register unchanged. Update DAC register with current contents of input register. Input register unchanged. Load DAC input register and update DAC register. Update DAC register with current contents of input register. Input register unchanged. Load DAC input register and update DAC register. After CS's rising edge and on LDAC's falling edge, update DAC register with current contents of input register. Input register unchanged. Load DAC input register. After CS's rising edge and on LDAC's falling edge, update DAC register. Load DAC input register and power down DAC. Load DAC input register, power down DAC, and update DAC register. Load DAC input register, power down DAC, and update DAC register. DATA BYTE Loaded Last D7........D0 LDAC Pin 6 COMMAND (Commands executed on CS's rising edge)
COMMANDS LOADING INPUT REGISTER ONLY COMMANDS LOADING DAC REGISTER X X X X X X X X X X X X 0 0 0 0 1 1 1 1 0 0 1 1 X X X X 0 1 0 1 XXXXXXXX 8-Bit DAC Data XXXXXXXX 8-Bit DAC Data X X 0 0
COMMANDS UTILIZING THE ASYNCHRONOUS LOAD FUNCTION X X X 0 1 1 X 0 XXXXXXXX 1
X
X
X
0
1
1
X
1
8-Bit DAC Data
1
COMMAND POWERING DOWN AND LOADING INPUT REGISTER ONLY X X X 1 0 X X 1 8-Bit DAC Data X COMMANDS POWERING DOWN AND UPDATING DAC REGISTER X X X X X X 1 1 1 1 0 1 X X 1 1 8-Bit DAC Data 8-Bit DAC Data X 0
COMMAND POWERING DOWN AND UTILIZING THE ASYNCHRONOUS LOAD FUNCTION X X X 1 1 1 X 1 8-Bit DAC Data 1 Load DAC input register and power down DAC. While powered down, on LDAC's falling edge, update DAC register.
X = Don't care
Table 5. Example Input Word
CONTROL BYTE Loaded First UB1 X UB2 X UB3 X C2 0 C1 1 C0 0 A1 0 A0 1 D7 1 D6 0 D5 0 D4 0 D3 0 D2 0 DATA BYTE Loaded Last D1 0 D0 0
X = Don't care
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+2.5V to +5.5V, Low-Power, Single/Dual, 8-Bit Voltage-Output DACs in MAX Package
Microprocessor Interfacing The MAX548A/MAX549A/MAX550A serial interface is SPI/QSPI and Microwire compatible. For SPI/QSPI, clear the CPOL and CPHA bits (CPOL = 0 and CPHA = 0). CPOL = 0 sets the clock idle state to zero, and CPHA = 0 changes data at SCLK's falling edge. This is the Microwire default condition. If a serial port is not available on your microprocessor, three bits of a parallel port can be used to emulate a serial port by bit manipulation. Operate the serial clock only when necessary, to minimize digital feedthrough at the DAC registers.
Careful PC board layout minimizes crosstalk in DAC registers, the reference, and the digital inputs. Separate analog traces by running ground traces between them. Make sure that high-frequency digital lines are not routed parallel to analog lines.
MAX548A/MAX549A/MAX550A
AC Considerations
Digital Feedthrough High-speed data at any of the digital input pins can couple through a DAC's internal stray package capacitance and cause noise (digital feedthrough) at the DAC output, even though LDAC and/or CS are held high (see Typical Operating Characteristics). Test digital feedthrough by holding LDAC and/or CS high and toggling the digital inputs from all 1s to all 0s. Analog Feedthrough Due to internal stray capacitance, higher frequency analog input signals at REF can couple to the output, even when the input digital code is all 0s. This condition is shown in the MAX549A/MAX550A Reference AC Feedthrough vs. Frequency graph in the Typical Operating Characteristics. Test analog feedthrough by setting all DAC outputs to 0V and sweeping REF.
__________Applications Information
Power-Supply and Ground Considerations
Connect GND to the highest quality ground available. Bypass VDD with a 0.1F to 0.22F capacitor to GND. The reference input can be used without bypassing. However, for optimum line/load-transient response and noise performance, bypass the reference input with a 0.1F to 4.7F capacitor to GND.
Table 6. Analog Output vs. Code
DAC CONTENTS D7 1 1 1 0 0 0 D6 1 0 0 1 0 0 D5 1 0 0 1 0 0 D4 1 0 0 1 0 0 D3 1 0 0 1 0 0 D2 1 0 0 1 0 0 D1 1 0 0 1 0 0 D0 1 1 0 1 1 0 ANALOG OUTPUT (V) +VREF(255 / 256) +VREF(129 / 256) +VREF(128 / 256) = +VREF / 2 +VREF(127 / 256) +VREF(1 / 256) 0
Note: 1LSB = VREF x 2-8 = VREF(1 / 256); ANALOG OUTPUT = +VREF(I / 256), where I = Integer Value of Digital Input.
_____________________________________________Pin Configurations (continued)
TOP VIEW
GND 1 OUTA 2 8 7 VDD REF OUTB SCLK GND 1 OUT 2 8 7 VDD REF LDAC SCLK
MAX549A
CS 3 DIN 4 6 5 CS 3 DIN 4
MAX550A
6 5
DIP/MAX
DIP/MAX
______________________________________________________________________________________
13
+2.5V to +5.5V, Low-Power, Single/Dual, 8-Bit Voltage-Output DACs in MAX Package MAX548A/MAX549A/MAX550A
_________________________________________________________Functional Diagram
VDD
8
DAC A INPUT REGISTER
8 DAC A REGISTER
8 DAC A R-2R LADDER
OUTA
DIN SCLK CS LDAC MAX548A/ MAX550A ONLY INPUT SHIFT REGISTER AND CONTROL 8 DAC B INPUT REGISTER 8 DAC B REGISTER VDD MAX548A ONLY 8 DAC B R-2R LADDER REF MAX549A/ MAX550A ONLY OUTB MAX548A/ MAX549A ONLY
MAX548A MAX549A MAX550A
GND
_Ordering Information (continued)
PART MAX549ACPA MAX549ACUA MAX549AC/D MAX549AEPA MAX549AEUA MAX550ACPA MAX550ACUA MAX550AC/D MAX550AEPA MAX550AEUA TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C PIN-PACKAGE 8 Plastic DIP 8 MAX Dice* 8 Plastic DIP 8 MAX 8 Plastic DIP 8 MAX Dice* 8 Plastic DIP 8 MAX
___________________Chip Information
TRANSISTOR COUNT: 1562
*Dice are specified at TA = +25C, DC parameters only.
14
______________________________________________________________________________________
+2.5V to +5.5V, Low-Power, Single/Dual, 8-Bit Voltage-Output DACs in MAX Package
________________________________________________________Package Information
PDIPN.EPS
MAX548A/MAX549A/MAX550A
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15
+2.5V to +5.5V, Low-Power, Single/Dual, 8-Bit Voltage-Output DACs in MAX Package MAX548A/MAX549A/MAX550A
___________________________________________Package Information (continued)
8LUMAXD.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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